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CN
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Product

Controller

Autonomous and controllable, stable and reliable
With the core positioning of independent controllability, high performance, and localization, we aim to create a domestically developed master controller with full chain independent research and development, covering hardware architecture design, firmware deep development, and system level testing, providing customers with complete solutions.
  • EMMC controller

    We have independently developed the eMMC controller, with complete control over the source code and patents. We also independently design and test programs for module production, conduct domestic chip production and packaging testing, support mainstream NAND, and are compatible with mainstream Host platforms.

    The controller is independently designed, with independent source code and patents, and supports customization.

    Adopting RISC-V open source architecture to avoid ARM licensing risks and achieve autonomous controllability.

    Fully compatible with ecological flash memory, compatible with six major original manufacturers including Samsung, Changjiang Storage, Hynix, Micron, Kaixia, and SanDisk.

    Collaborate with manufacturers such as Changjiang Storage to develop nationwide production of xMCP products through adaptation certification.

    Vehicle/industrial grade design, suitable for harsh environments in multiple scenarios including consumer grade, industrial control grade, and vehicle grade.

    Equipped with advanced error correction engine, low-power design, balancing performance and energy efficiency.

  • UFS controller

    Our self-developed UFS controller is designed to provide high-performance, high-capacity, and low-power storage solutions for mobile devices. It supports mainstream NAND and is compatible with mainstream Host platforms, with high performance, high stability, low power consumption, and strong compatibility.

    The earliest to receive support for national encryption algorithms (SM2/SM3/SM4), with built-in AES and national encryption hardware engine.

    Supports mainstream NAND, compatible with mainstream Host platforms, and has strong compatibility.

    Based on advanced process hardware design, adopting a 2-channel+4-CE low-power architecture.

    Provide customized hardware instruction sets, support machine learning, scene optimization, and adapt to diverse application scenarios.

    Built in LDPC error correction engine, achieving the lowest power consumption and efficient error correction.

    High erase count, meeting the durability requirements of mobile and portable devices.

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